Fujitsu F2MC-16LX Hardware Manual page 96

CHAPTER 3 INTERRUPT
Buffer address Pointer (BAP)
The buffer address pointer (BAP), a 24-bit register, contains the address used for the next attempt of
transfer by EI
channels to transfer data between any address of 16 Mbytes and I/O. If the BF bit (BAP update/fix selection
bit of EI
bit (BAPM, BAPL) will change in the BAP. The higher 8-bit (BAPH) will be unchanged in this case.
Figure 3.6-6 shows the BAP configuration.
bit23
BAP
R/W : Readable/Writable
X : Indeterminate
Note:
In the I/O address pointer (IOA), the 000000
In the buffer address pointer (BAP), the 000000
The maximum transfer count which may be specified in the data counter (DCT) is 65,536 (64
Kbytes).
80
2
OS. The BAP is provided independently for the EI
2
OS status register) of the EI
Figure 3.6-6 Configuration of Buffer address Pointer (BAP)
bit16 bit15
BAPH
BAPM
(R/W)
(R/W)
2
OS status register (ISCS) is set to "updated", only the low order 16-
bit7
bit8
bit0
BAPL
(R/W)
to 00FFFF area is available for specification.
H H
to FFFFFF
H H
2
OS channels to enable the EI
Initial value
XXXXXXXXXXXXXXXXXXXXXXXX
area is available for specification.
2
OS
B