Fujitsu F2MC-16LX Hardware Manual page 622

APPENDIX
Table A-1 I/O Map (5/9)
Address
2
00007C
I C bus status register 2
H
00007D 2
I C bus control register 2
H
2
00007E
I C clock control register 2
H
2
00007F
I C bus address register 2
H
2
000080
I C bus data register 2
H
000081
H
to
000085
H
000086
Low order of timer counter data register
H
000087
High order of timer counter data register
H
000088
Timer control status register, lower
H
000089
Timer control status register, higher
H
00008A
Low order of compare clear register
H
00008B
High order of compare clear register
H
00008C
H
to
00009A
H
DMA descriptor channel specification
00009B
H
register
00009C
Low order of DMA status register
H
00009D
Low order of DMA status register
H
Program address detection control
00009E
H
status register
Delay interruption factor generation/release
00009F
H
register
Low-power consumption mode
0000A0
H
control register
0000A1
Clock select register
H
0000A2
H
to
0000A3
H
0000A4
DMA stop status register
H
0000A5
H
to
0000A7
H
0000A8
Watchdog timer control register
H
0000A9
Timebase timer control register
H
0000AA
Watch timer control register
H
0000AB
H
606
Registers Abbreviation Access
IBSR2 R
IBCR2 R/W
ICCR2 R/W
IADR2 R/W
IDAR2 R/W
Use prohibited
R/W
TCDT
R/W
R/W
TCCS
R/W
R/W
CPCLR
R/W
Use prohibited
DCSR R/W
DSRL R/W
DSRH R/W
PACSR R/W
DIRR R/W
LPMCR R/W,W
CKSCR R/W,R
Use prohibited
DSSR R/W
Use prohibited
WDTC R,W
TBTC R/W,W
WTC R/W,R
Use prohibited
Release Initial value
00000000
00000000
2
XX0XXXXX
I C interface ch2
XXXXXXXX
XXXXXXXX
00000000
00000000
00000000
16-bit free-run
timer
0XX00000
XXXXXXXX
XXXXXXXX
00000000
µDMAC
00000000
00000000
Address compare
00000000
detection
Delayed interrupt -------0
Low power
00011000
consumption
Clock 11111100
µDMAC
00000000
Watchdog
X-XXX111
Timers
Timebase
1--00100
Timers
Watch timer 10001000