Fujitsu F2MC-16LX Hardware Manual page 152

CHAPTER 5 CLOCK
Transition from PLL clock mode to sub clock mode
If the sub clock selection bit (SCS) of the clock selection register (CKSCR) is rewritten from "1" to "0"
while in the PLL clock mode, the mode changes from PLL clock to sub clock.
Transition from sub clock mode to PLL clock mode
If the SCS bit of the CKSCR is rewritten from "0" to "1" while in the sub clock mode, the mode changes
from sub clock to PLL clock after the main clock oscillation stabilization wait time. The oscillation
stabilization wait time can be selected using the oscillation stabilization wait time selection bits (WS1,
WS0) of the CKSCR.
Note:
Even if the PLL clock selection (MCS) or SCS bit of the CKSCR is rewritten, the machine clock is not
switched immediately. If a resource which depends on the machine clock needs to be operated, refer
the PLL clock indicator bit (MCM) and sub clock indicator bit (SCM) of the CKSCR to check that the
machine clock has been switched, before beginning the operation.
If both the SCS and MCS bits are "0", the higher priority is given to SCS and the sub clock mode is
entered.
If the clock mode is switched, the mode must not be switched to another clock mode or the low-
power consumption mode until completion of the switching. Completion of the switching can be
checked by referring the MCM and SCM bits of the CKSCR.
Selection of PLL Clock Multiplication Rate
One of the three PLL clock frequency multiplier from 1 to 4 times can be selected by writing "00
"10 " to the CS1 and CS0 bits of the CKSCR. "11
B
Machine Clock
The PLL clock, main clock, and sub clock output from the PLL multiplying circuit are used as machine
clocks. These machine are clocks supplied to the CPU or peripheral function. One of the main, PLL, and
sub clock modes can be selected by writing the CKSCR of MCS and SCS bit.
Figure 5.4-1 shows the transition chart of the machine clock selection.
136
" is a set interdiction.
B
" to
B