Fujitsu F2MC-16LX Hardware Manual page 321

IN direction (host PC → device) forwarding
Host PC
Device
Device
DRQ flag *
Host PC
CPU clear
DMAE
DRQIE
DRQ
DER(Enx)
DMA sending buffer write
(DATA0)
In IN- direction transfer, a USB device must perform processes in the follows steps:
1. When the DRQ flag is set and enters the interrupt process, it sets the number of pieces of data to be
transferred in an IN packet in the data counter register DDCT of DMA, enables DMA with the DER
register, and start transfer.
2. Once DMA transfer has been completed, it clears the corresponding DRQ flag in the EP1S to EP5S
registers and the corresponding interrupt factor flag in the DSR register of µDMAC and returns from the
interrupt process.
*:EP1 to EP5 consists of the double buffers, it can be cleared only when one buffer that is not being
accessed has already data written into it and data is written into another buffer that is being accessed and
cannot be cleared even though "0" is written to it when one buffer that is not being accessed is empty
(Dotted line status). It continuously enters the DRQ interrupt process.
Data Number automatic Transfer Mode
It sets the total number of pieces of data to be transferred in DMA and sets the transfer enable bit in
advance. When DMAE is enabled and the DRQ is set after transfer from the HOST has been completed,
the interrupt cause is automatically cleared when data whose number of pieces is equal to the PKS in the
EP1 to EP5 control registers (EPxC) has been transferred (Whether the DRQ flag is actually cleared
depends on the fact that both buffers in a double buffer are empty or full). Subsequently, when transfer
from the HOST has been completed, repeat the similar process until data equivalent to the number of pieces
of transfer data predefined in DMA. has been transferred. Meanwhile, any intervention from CPU is not
required, and transfer will be completed with only one setting, which is the automatic transfer mode. If the
device performs the next transfer, it sets µDMAC again and enables DMA when a CPU interrupt is raised
when the last data has been transferred, and returns from the CPU interrupt. Since the data number
automatic transfer mode is used for DMAE=1, only buffer access to endpoint 1 to endpoint5 is enabled.
Timing by which the buffer is accessed in OUT direction and IN direction is shown as follows.
Figure 13.4-10 IN Packet Forwarding
IN packet
IN ACK
DRQ flag *
DATA0
CPU clear
DMA sending buffer write
(DATA1)
CHAPTER 13 USB FUNCTION
IN packet
IN ACK
DATA1
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