Fujitsu F2MC-16LX Hardware Manual page 219

Analog Input Enable Register (ADER0,ADER1)
Figure 8.2-5 shows the bit configuration of the analog input permission registers (ADER0, ADER1).
Figure 8.2-5 Bit Configuration of analog Input Enable Register (ADER0, ADER1)
ADER0
00001E
Address :
ADER1
00001F
Address :
The analog input enable registers (ADER0, ADER1) control each pin of port 7, 8 as follows;
• 0: Entering in the port I/O mode
• 1: Entering in the analog input mode. This bit becomes 0 after a reset.
7 6 5
ADE07 ADE06 ADE05 ADE04 ADE03 ADE02 ADE01 ADE00
H
15 14 13
ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE09 ADE08
H
4 3 2 1
12 11 10 9
CHAPTER 8 I/O PORT
0
Initial value
Access
11111111
R/W
B
8
R/W
11111111
B
203