Fujitsu F2MC-16LX Hardware Manual page 212

CHAPTER 7 MODE SETTING
Figure 7.5-7 Timing Chart of Holding Function (Non-multiplex Mode)
Read cycle
P57/CLK
P54/HRQ
P55/HAK
P53/WRH
P52/WRL
P51/RD
P50/ALE
A23 to A16
A15 to A08
A07 to A00
D15 to D08/
AD15 to AD08
D07 to D00/
AD07 to AD00
Read data
Multiple Mode
Figure 7.5-8 shows the timing chart of the hold function of the multiplex mode in the external data bus 16-
bit mode.
Figure 7.5-8 Timing Chart of Holding Function (Multiplex Mode)
Read cycle
P57/CLK
P54/HRQ
P55/HAK
P53/WRH
P52/WRL
P51/RD
P50/ALE
A23 to A16
A15 to A08
A07 to A00
D15 to D08/
AD15 to AD08
D07 to D00/
AD07 to AD00
Note:
When "H" level is inputted to the P54/HRQ pin, it is retained until P55 pin becomes "L" level.
196
Hold cycle
(Address)
(Address)
(Address)
Hold cycle
(Address)
(Port data)
(Port data)
Read data
Write cycle
(Address)
(Address)
(Address)
Write data
Write cycle
(Address)
(Address)
(Address)
Write data