Fujitsu F2MC-16LX Hardware Manual page 232

CHAPTER 9 TIMEBASE TIMER
Operations of Timebase Timer
Operations in the following situations are shown in Figure 9.6-1.
• At a power-on reset occurs.
• At a transition to sleep mode during the operation of interval timer function
• At a transition to stop mode.
• At a counter clear request occurs.
The transition to the stop mode clears the timebase timer, terminating operations. Upon the recovery from
the stop mode, oscillation stabilization wait time is counted with the timebase timer.
Counter value
Oscillation
stabilization
wait overflow
TBOF bit
TBIE bit
SLP bit
(LPMCR register)
STP bit
(LPMCR register)
When setting "11
B
timer control register (2
: Oscillation stabilization wait time
: Oscillation clock
HCLK
216
Figure 9.6-1 Operations of Timebase Timer
3FFFF
H
00000
H
CPU operation
start
Power-on reset
(Option)
Interval interrupt sleep cancellation
" to interval time selection bit (TBTC: TBC1, TBC0) of timebase
19
/HCLK)
Clear by transition
to the stop mode
Interval cycle
( )
TBTC : TBC1, TBC0=11
B
Clear by interrupt routine
Sleep
Stop cancellation by External interrupt
Counter clear
(
TBTC : TBR=0
Stop
)