Pwc Ratio Of Dividing Frequency Control Register (Divr) - Fujitsu F2MC-16LX Hardware Manual

15.2.3 PWC Ratio of Dividing Frequency Control Register
(DIVR)
Configuration and function of PWC Ratio of dividing frequency control register (DIVR)
are described.

PWC Ratio of Dividing Frequency Control Register (DIVR)

Figure 15.2-4 shows the bit configuration of a PWC ratio of dividing frequency control register (DIVR).
Figure 15.2-4 Bit Configuration of PWC Ratio of Dividing Frequency Control Register (DIVR)
7
−
000060
H
−
( )
R/W : Readable/Writable
−
: Undefined
[bit 7 to bit 2] Undefinition bit
The reading value is irregular. No effect on writing.
[bit 1, bit 0] DIV1, DIV0 (division ratio selection)
This register is used in the division cycle measurement mode (PWCSR bit 2.1.0: MOD2.MOD1.MOD0
= 001
In the division cycle measurement mode, pulses input to the measurement terminal are divided by the
division ratio set in the DIVR register and a single cycle width is measured after dividing.
Table 15.2-7 Division Ratio Selection
DIV1
0
0
1
1
• Initialized to "00
• Reading and writing are allowed.
Note:
Rewriting after the startup is an interdiction. Always perform the write operation before start or after
stop.
6 5 4 3
− − − −
− − − −
( ) ( ) ( ) ( )
) and has no meaning in the other mode else.
B
DIV0
0
1
0
1
" at reset.
B
2 1 0
DIVR
−
DIV1 DIV0
PWC ratio of dividing frequency control register
−
Initial value ------00
( ) (R/W) (R/W)
Count clock selection
4-dividing frequency [Initial value]
16-frequency division
64-frequency division
256-frequency division
CHAPTER 15 PWC TIMER
B
365