Fujitsu F2MC-16LX Hardware Manual page 553

Acknowledge
The receiver send the acknowledge to the sender. During data reception, ACK bit can specify
acknowledgement is necessary or not. During the data sending, the acknowledge from the receiver is stored
in the LRB bit.
If the sender as slave does not receive any acknowledgement from the receiver as master, TRX becomes
"0", resulting in the slave receiving mode. This allows the master to generate the stop condition when the
slave releases the SCL line.
Bus Error
If the following conditions exist, it will be considered as bus error, and the I
stopped state.
• Detecting of violation of the basic rules on I
• Stop condition detection at master
• Detecting of violation of the basic rules on I
The Others
Processing after arbitration lost is detected
After arbitration lost occurs, must decide if it is addressed or not by software.
Once arbitration lost occurs, it becomes slave from the viewpoint of hardware. After one byte of data
transfer both CLK line and DATA line are pulled to "L". For this reason, if addressing is done, CLK line
and DATA line should be released after slave transmission or slave reception is ready. if no addressing is
done, then CLK line and DATA line should be immediately released. (Software is responsible for this all.)
Interruption factor when arbitration lost is detected
When arbitration lost is detected, causes of interrupts are not issued immediately but after one byte of data
has been transferred.
When arbitration lost is detected, it becomes slave from the viewpoint of hardware. Even if so, it outputs 9
clocks in all in order to issue causes of interrupts. For this reason, causes and interrupts are not immediately
issued, so no processing is allowed after arbitration lost.
Interrupt condition
It is specified that I
completes or if the conditions of interrupts are satisfied.
Each flag should be checked within the interrupt routine, since multiple conditions of interrupts is
identified based on one interrupt. Multiple conditions of interrupts on completion of one byte transfer is as
follows.
• When it is a bus master
• When it is a slave that the address is done
• When you receive the General call address
• When arbitration lost has occurred.
Transfer rate
2
Note that I C bus can support up to 100 kHz of the serial clock frequency of transmission.
2
C bus has one interrupt and causes of interrupts are issued once one byte of transfer
CHAPTER 22 I
2
C bus during data transfer (including Ack bit)
2
C bus in bus idle.
2
C INTERFACE
2
C interface will be in the
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