Fujitsu F2MC-16LX Hardware Manual page 694

16-bit microcontroller mb90330 series
Hide thumbs Also See for F2MC-16LX:
Table of Contents

Advertisement

INDEX
External Memory
I/O Signal Terminal of External Memory Access
External Memory Access
External Memory Access Control Signal
External Pin
Operation of External Pin in Each Mode
External Reset Pin
Block Diagram of External Reset Pin
External Shift Clock
External Shift Clock Mode
External USB
Connected Detection of External USB Device
Disconnection Status,Connection Status of the External
.......................................... 337
USB Device
F
2
F
MC-16LX
2
F
MC-16LX Instruction List
Fetch
....................................................... 120
Mode Fetch
Flag
Hardware Sequence Flag
Receive Interrupt Generation and Flag Set Timing
State Transition of Data Polling Flag (DQ7)
Transition State of Sector Erasing Timer Flag
................................................. 575
(DQ3)
Transition State of Timing Limit Over Flag (DQ5)
Transition State of Toggle Bit 2 Flag (DQ2)
Transition State of Toggle Bit Flag (DQ6)
Transmit Interrupt Generation and Flag Set Timing
Flag Change Suppression Prefix
Flag Change Suppression Prefix (NCC)
Flash Memory
Erasing All Data from Flash Memory (Chip Erase)
Erasing Any Data in Flash Memory
(Sector Erasing)
Features of 3M-bit Flash Memory
Flash Memory Sector Erase Resumption
Flash Memory Sector Erase Suspension
Method for Writing/deleting Flash Memory
Read/Reset State in Flash Memory
Write/Erase of Flash Memory
Writing Data to Flash Memory
Writing Procedure of Flash Memory
Flash Memory Control Status Register
Flash Memory Control Status Register
....................................... 564, 566
(FMCS)
Flash Microcomputer Programmer
Example of Minimum Connection to Flash Microcomputer
Programmer (when Using User Power)
Flash Microcomputer Programmer System
Flash Microcomputer Programmer System
FMCS
Flash Memory Control Status Register
....................................... 564, 566
(FMCS)
FRAME Setting Register
FRAME Setting Register (HFRAME)
678
........ 182
.................. 189
...................181
....................... 118
.................................... 469
........... 337
................................. 635
......................................570
......496
.............. 572
..... 574
.............. 576
................ 573
.... 498
..................... 44
..... 581
..................................... 582
........................... 564
.................. 585
...................584
.............. 564
.......................... 578
................................ 577
............................... 579
........................ 579
....... 595
................ 591
...................... 333
Free-run Timer
Block Diagram of 16-bit Free-run Timer
Count Timing of Free-run Timer
Free-run Timer Clear Timing
(for a Match with Compare Register 0)
Operation of 16-bit Free-run Timer
Register List of 16-bit Free-run Timer
Fujitsu Standard
Pins Used for Fujitsu Standard Serial On-board
........................................ 589
Programming
G
General-purpose Register
General-purpose Register
General-purpose Registers
General-purpose Registers (Register Bank)
H
HACR
External Address Output Control Register
.............................................. 185
(HACR)
HADR
Host Address Register (HADR)
Handshake Packet
............................................... 343
Handshake Packet
Hardware Component
Initial Value of Hardware Component
Hardware Interrupt
Construction of Hardware Interrupt
Function of Hardware Interrupt
Hardware Interrupt Processing Time
Hardware Interrupt Suppression
Operation Flow of Hardware Interrupt
Operation of Hardware Interrupt
Procedure for Using a Hardware Interrupt
Return from Hardware Interrupt
Start of Hardware Interrupt
Hardware Sequence
Hardware Sequence Flag
HCNT
Host Control Register 0,1(HCNT0/HCNT1)
HEOF
EOF Setting Register (HEOF)
HERR
Host Error Status Register (HERR)
HFCOMP
SOF Interruption FRAME Comparison Register
.......................................... 329
(HFCOMP)
HFRAME
FRAME Setting Register (HFRAME)
HIRQ
Host Interruption Register (HIRQ)
Holding Function
Operation of Holding Function
Host
Diversity with USB Host
.................. 242
............................ 261
....... 261
......................... 256
..................... 241
....................................... 33
................. 42
............................. 331
..................... 419
........................... 62
................................ 61
......................... 70
............................... 62
....................... 66
.............................. 65
.................. 67
............................... 64
..................................... 64
...................................... 570
............. 316
............................... 332
......................... 323
..................... 333
.......................... 320
.............................. 195
...................................... 311

Advertisement

Table of Contents
loading

Table of Contents