Fujitsu F2MC-16LX Hardware Manual page 695

............................................. 303
Wake-up from Host
Host Address Register
Host Address Register (HADR)
Host Control Register
Host Control Register 0,1(HCNT0/HCNT1)
Host Error Status Register
Host Error Status Register (HERR)
Host Interruption Register
Host Interruption Register (HIRQ)
Host State Status Register
Host State Status Register (HSTATE)
Host Token Endpoint Register
Host Token Endpoint Register (HTOKEN)
HRTIMER
Retry Timer Setting Register (HRTIMER)
HSTATE
Host State Status Register (HSTATE)
HTOKEN
Host Token Endpoint Register (HTOKEN)
I
I/O Circuit
.................................................. 18
I/O Circuit Types
I/O Map
........................................................... 602
I/O Map
I/O Port
............................................... 199
I/O Port Registers
I/O Ports
.......................................... 198
Functions of I/O Ports
I/O Register Address Pointer
I/O Register Address Pointer (IOA)
I/O Signal Terminal
I/O Signal Terminal of External Memory Access
I/O Timer
Configuration Function of 16-bit I/O Timer
Operation and Timing of 16-bit I/O Timer
Register Configuration of 16-bit I/O Timer
2
I
C Bus Address Register
2
I C Bus Address Register 0 to 2
(IADR0 to IADR2)
2
I
C Bus Clock Control Register
2
I C Bus Clock Control Register 0 to 2
(ICCR0 to ICCR2)
2
I
C Bus Control Register
2
I C Bus Control Register 0 to 2
(IBCR0 to IBCR2)
2
Notes on Use of I C Bus Control Register 0 to 2
(IBCR0 to IBCR2)
2
I
C Bus Data Register
2
I C Bus Data Register 0 to 2 (IDAR0 to IDAR2)
2
I
C Bus Status Register
2
I C Bus Status Register 0 to 2 (IBSR0 to IBSR2)
2
I
C Interface
2
Flow of I C Interface Mode Transitions
2
......................................... 522
I C Interface Function
............................. 331
............. 316
......................... 323
.......................... 320
..................... 326
............... 334
................ 330
..................... 326
............... 334
.......................... 78
....... 182
.............. 238
................ 255
............... 240
................................ 534
................................. 532
................................. 527
................................. 531
....... 535
....... 525
................... 540
2
Operation Flow of I C Interface
2
Register List of I C Interface
2
Transfer Flow of I C Interface
IADR
2
I C Bus Address Register 0 to 2
(IADR0 to IADR2)
IBCR
2
I C Bus Control Register 0 to 2
(IBCR0 to IBCR2)
2
Notes on Use of I C Bus Control Register 0 to 2
(IBCR0 to IBCR2)
IBSR
2
I C Bus Status Register 0 to 2 (IBSR0 to IBSR2)
ICCR
2
I C Bus Clock Control Register 0 to 2
(ICCR0 to ICCR2)
ICR
Configuration of Interrupt Control Register (ICR)
Interrupt Control Registers (ICR00 to ICR15)
ICS
Control Status Registers (ICS01,ICS23)
IDAR
2
I C Bus Data Register 0 to 2 (IDAR0 to IDAR2)
ILM
Interrupt Level Mask Register (ILM)
IN
.........................................353
IN,OUT,SETUP Token
Indirect Addressing
..............................................623
Indirect Addressing
Initial Value
Direct Page Register (DPR)<Initial Value:01
Initial Value of Hardware Component
Program Bank Register (PCB)<Initial Value: Value in Reset
..................................................40
Vector>
Input Capture
Block Diagram of Input Capture
Example of Taking Timing of Input Capture
.....................................................252
Input Capture
List of Register of Input Capture
Input Capture Data Register
Input Capture Data Registers (IPCP0 to IPCP3)
Input Pulse Width
Minimum Input Pulse Width
Instruction
Description of Instruction Presentation Items and
...............................................633
Symbols
Exception due to Execution of an Undefined
............................................103
Instruction
Execution of an Undefined Instruction
2
F MC-16LX Instruction List
................................................615
Instruction Types
Instruction Map
Structure of Instruction Map
Instructions
Constraints on Interrupt Suppression Instructions and
Prefix Instructions
INDEX
..............................541
.................................524
................................538
.................................534
..................................527
..................................531
........525
..................................532
.........58
..............56
...................253
........535
.........................37
...........41
>
H
......................419
.............................252
..............260
.............................253
..........253
..................................378
.....................103
..................................635
..................................649
....................................46
679