Fujitsu F2MC-16LX Hardware Manual page 642

APPENDIX
Program counter relative branch address (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of the addition exceeds 16 bits, the bank register is not incremented/
decremented and the excess portion is ignored. This will result in a closed address space within the 64-
Kbyte bank. This addressing mode is used for conditional/unconditional branch instructions. Bit 123 to Bit
16 of the address are specified by the program bank register (PCB).
Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
626
(This instruction causes an unconditional relativity branch)
BRA 3B20H
Before execution
PC 3 C 2 0
After execution PC 3 B 2 0
Figure B.4-8 Configuration of the Register List
MSB
RW7 RW6 RW5
A register is selected when the corresponding bit
is 1 and not selected when the bit is 0.
Figure B.4-9 Example of Register List (rlist)
(This instruction transfers memory data indicated
POPW RW0, RW4
by the SP to multiple word registers indicated
by the register list.)
SP 3 4 F A
× × × ×
RW0
× × × ×
RW1
× × × ×
RW2
× × × ×
RW3
× × × ×
RW4
× × × ×
RW5
× × × ×
RW6
× × × ×
RW7
Memory space
0 4
0 3
0 2
SP
0 1
Before execution
4F3C22
PCB 4 F
4F3C21
4F3C20
PCB 4 F
4F3B20
LSB
RW4 RW3 RW2 RW1 RW0
SP 3 4 F E
RW0 0 2 0 1
× × × ×
RW1
× × × ×
RW2
× × × ×
RW3
0 4 0 3
RW4
× × × ×
RW5
× × × ×
RW6
× × × ×
RW7
Memory space
34FE
H
34FD SP 0 4
H
0 3
34FC
H
34FB 0 2
H
34FA 0 1
H
After execution
Memory space
F F
H
F E
H
6 0
H
Next
instruction
H
BRA 3B20H
34FE
H
34FD
H
34FC
H
34FB
H
34FA
H