Fujitsu F2MC-16LX Hardware Manual page 633

Effective Address Field
Table B.2-1 shows the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code Representation
00 R0
01 R1
02 R2
03 R3
04 R4
05 R5
06 R6
07 R7
08 @RW0
09 @RW1
0A @RW2
0B @RW3
0C @RW0+
0D @RW1+
0E @RW2+
0F @RW3+
10 @RW0+disp8
11 @RW1+disp8
12 @RW2+disp8
13 @RW3+disp8
14 @RW4+disp8
15 @RW5+disp8
16 @RW6+disp8
17 @RW7+disp8
18 @RW0+disp16
19 @RW1+disp16
1A @RW2+disp16
1B @RW3+disp16
1C @RW0+RW7
1D @RW1+RW7
1E @PC+disp16
1F addr16
RW0 RL0
RW1 (RL0) Register direct
RW2 RL1 "ea" corresponds to the following models
RW3 (RL1) from left, sequentially.
• Byte
RW4 RL2
• word
RW5 (RL2)
• long word
RW6 RL3
RW7 (RL3)
Register indirect
With post increment
Register indirect
With 8-bit displacement
Register indirect
With16-bit displacement
Register indirect
Register indirect with index
Register indirect with index
PC indirect with16-bit displacement
Direct address
Address format
Appendix B Instruction
Default bank
None
DTB
DTB
ADB
SPB
DTB
DTB
ADB
SPB
DTB
DTB
ADB
SPB
DTB
DTB
ADB
SPB
DTB
DTB
ADB
SPB
DTB
DTB
PCB
DTB
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