Fujitsu F2MC-16LX Hardware Manual page 692

INDEX
Each Register of DMA Descriptor
Detect Address
......................................... 555
Setting Detect Address
Detect Address Setting Registers
Detect Address Setting Registers (PADR0,PADR1)
Device
................................................ 352
Cutting of Device
Devices
Precautions when Handling Devices
DIOAH
DMA I/O Register Address Pointer
(DIOAH/DIOAL)
DIOAL
DMA I/O Register Address Pointer
(DIOAH/DIOAL)
Direct Addressing
............................................... 618
Direct Addressing
Direct Page Register
Direct Page Register (DPR)<Initial Value:01
Disconnection Status
Disconnection Status,Connection Status of the External
.......................................... 337
USB Device
DIVR
PWC Ratio of Dividing Frequency Control Register
................................................ 365
(DIVR)
DMA
Each Register of DMA Descriptor
DMA Buffer Address Pointer
DMA Buffer Address Pointer
(DBAPH/DBAPM/DBAPL)
DMA Control Register
DMA Control Register (DMACS)
DMA Data Counter
About the Set Value of DMA Data Counter
(DDCTH/DDCTL)
DMA Data Counter (DDCTH/DDCTL)
DMA Descriptor Channel Specification Register
DMA Descriptor Channel Specification Register
................................................. 90
(DCSR)
DMA Descriptor Window Register
Configuration of DMA Descriptor Window Register
................................................ 95
(DDWR)
DMA I/O Register Address Pointer
DMA I/O Register Address Pointer
(DIOAH/DIOAL)
DMA Permission Register
DMA Permission Register (DERH/DERL)
DMA Status Register
Bit Configuration of DMA Status Register
(DSRH/DSRL)
DMA Stop Status Register
DMA Stop Status Register (DSSR)
DMACS
DMA Control Register (DMACS)
DPR
Direct Page Register (DPR)<Initial Value:01
676
............................ 95
.... 553
.......................... 21
.................................... 97
.................................... 97
........... 41
>
H
............................ 95
..................... 100
............................. 98
................................... 96
..................... 96
.................................... 97
................. 94
........................................ 92
........................... 93
............................. 98
........... 41
>
H
DQ2
Transition State of Toggle Bit 2 Flag (DQ2)
DQ3
Transition State of Sector Erasing Timer Flag
................................................. 575
(DQ3)
DQ5
Transition State of Timing Limit Over Flag (DQ5)
DQ6
Transition State of Toggle Bit Flag (DQ6)
DQ7
State Transition of Data Polling Flag (DQ7)
DSRH
Bit Configuration of DMA Status Register
(DSRH/DSRL)
DSRL
Bit Configuration of DMA Status Register
(DSRH/DSRL)
DSSR
DMA Stop Status Register (DSSR)
DTP
Block Diagram of DTP/External Interrupt
............................................... 425
Operation of DTP
Operation Process of DTP/External Interrupt
Overview of DTP/External Interrupt
Register List of DTP/external Interrupt
DTP/Interruption Factor Register
DTP/Interruption Factor Register (EIRR: External Interrupt
Request Register)
DTP/interruption Permission Register
DTP/interruption Permission Register (ENIR: Enable
Interrupt Request Register)
E
2
E
PROM
2
....................................... 556
E PROM Memory Map
Operation of Address Match Detection Function
at Storing Patch Program in E
System Configuration and E
.................................................... 556
Map
Effective Address
........................................ 632
Effective Address Field
2
EI
OS
Configuration of Extended Intelligent I/O Service
2
(EI OS) Descriptor (ISD)
Conversion Operation Using µDMAC or EI
2
Example of EI OS Start Program in Continuous
.......................................... 452, 455
Mode
2
Example of EI OS Start Program in Single
.................................................. 449
Mode
Extended Intelligent I/O Service (EI
Extended Intelligent I/O Service (EI
Time (Time for One Transfer)
Extended Intelligent I/O Service (EI
Register (ISCS)
Interrupt of Timebase Timer and EI
2
Interruption of UART,EI
Operation of Extended Intelligent I/O Service
2
........................................... 75, 81
(EI OS)
............. 576
..... 574
................ 573
............. 572
........................................ 92
........................................ 92
........................... 93
................ 422
............ 427
....................... 422
.................... 423
.................................. 424
...................... 423
2
........ 559
PROM
2
PROM Memory
.......................... 76
2
........ 445
OS
2
................... 74
OS)
2
OS) Processing
.................... 83
2
OS) Status
....................................... 79
2 OS, µDMAC
...... 212
OS, and µDMAC
.............. 495