Fujitsu F2MC-16LX Hardware Manual page 504

CHAPTER 21 UART
Table 21.4-3 Description of Each Bit of the Serial Status Registers 0 to 3 (SSR0 to SSR3)
Bit name
PE:
bit 15 Parity error flag
bit
ORE:
bit 14 Overrun error flag
bit
FRE:
bit 13 Framing error
flag bit
RDRF:
bit 12 Receive data full
flag bit
TDRE:
bit 11 Transmission data
empty flag bit
BDS:
bit 10 Transfer direction
selection bit
488
• Detect a parity error of receiving data.
• This bit is set to "1" when a parity error occurs.
• This is cleared by writing "0" in the receiving error clear bit (SCR0 to SCR3: REC).
• When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), a receiving interrupt
request is generated if a parity error occurs
• When the parity error flag bit is set (SSR0 to SSR3: PE = 1), data in serial input data
register is invalid.
• Detect an overrun error in receiving.
• This bit is set to "1" when an overrun error occurs.
• This is cleared by writing "0" in the receiving error flag clear bit (SCR0 to SCR3: REC).
• When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), a receiving interrupt
request is generated if a overrun error occurs.
• When the overrun error flag bit is set (SSR0 to SSR3: ORE = 1), data in serial input data
register is invalid.
• Detect a framing error of receive data.
• This bit is set to "1" when a framing error occurs.
• This is cleared by writing "0" in the receiving error clear bit (SCR0 to SCR3: REC).
• When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), a receiving interrupt
request is generated if a framing error occurs.
• When the framing error flag bit is set (SSR0 to SSR3: FRE = 1), data in serial input data
register is invalid.
• Show the status of the serial input data register.
• When received data is loaded to serial input data register 0 to 3 (SIDR0 to SIDR3), "1" is
set.
• This bit is cleared to "0" when data is read from the serial input data register 0 to 3
(SIDR0 to SIDR3).
• When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), a receiving interrupt
request are generated if receiving data is loaded to the serial input data registers (SIDR0
to SIDR3).
• Show the status of the serial output data register 0 to 3 (SODR0 to SODR3).
• The bit is cleared to "0" by writing sending data to the serial output data registers 0 to 3
(SODR0 to SODR3).
• This bit is set to "1" when data is loaded to the send shift register and transmission starts.
• When sending interrupts are enabled (SSR0 to SSR3: TIE=1) and if the data that has
written to the serial output data registers 0 to 3 (SODR0 to SODR3) is transferred to the
sending shift register, then a sending interrupt request is generated.
• This bit sets the direction of serial data transfer.
• When set to "0": Serial data is transferred from the LSB bit first (LSB first).
• When set to "1": Serial data is transferred from the MSB bit first (MSB first).
Note:
If BDS bit is rewritten after the completion of the access to the register, the rewritten
data will be invalid, since in reading to the serial input data register and in writing to
the serial output data register, the LSB data and the MSB data are turned upside
down.
Functions