Fujitsu F2MC-16LX Hardware Manual page 524

CHAPTER 21 UART
Figure 21.7-2 Sending and Receiving Data when Parity Bits are Valid
: Start bit
ST
SP : Stop bit
NOTE : Parity cannot be used in operation mode 1, 2.
508
SIN0 to SIN3 ST
1 0 1 1 0 0 0
ST
SOT0 to SOT3
1 0 1 1 0 0 1
SOT0 to SOT3
ST
1 0 1 1 0 0 0
When receiving by even parity
SP
Parity error generation
(SCR0 to SCR3 : P=0)
Transfer even parity
SP
(SCR0 to SCR3 : P=0)
Transfer odd parity
SP
(SCR0 to SCR3 : P=1)
Data parity