Fujitsu F2MC-16LX Hardware Manual page 44

CHAPTER 2 CPU
Address Generation Type
2
In F MC-16LX CPU, there is two address generation method. One is the linear addressing to specify the
entire 24-bit address by the instruction and the other is the bank addressing to specify the upper 8-bit
address and the lower 16-bit address by an appropriate bank register and the instruction, respectively.
There are two types of linear addressing, the method to directly specify the 24-bit address by the operand
and the method to quote the lower 24 bits as the address out of 32-bit general-purpose register content.
Linear addressing (24 bit operand designation)
Figure 2.2-2 shows the example of the linear addressing specified by the 24-bit operand.
JMPP 123456
Old program counter
New program counter
Linear addressing (indirectly specified by the 32-bit register)
Figure 2.2-3 shows the example of the linear addressing indirectly specified by the 32-bit register.
Figure 2.2-3 Linear addressing (Indirectly Specified by the 32-bit Register)
MOV A, @RL1+7
28
Figure 2.2-2 Linear addressing (24-bit Operand Designation)
H
17 452D
12 3456
Old AL
XXXX
New AL
003A
17452D
H
123456
H
090700
H
+7
RL1
(Upper 8-bit are ignored)
JMPP 123456
H
Next instruction
3A
240906F9