Uart Prescaler Control Register 0 To 3 (Utcr0 To Utcr3) And Uart Prescaler Reload Register 0 To 3 (Utrlr0 To Utrlr3) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 21 UART
21.4.5 UART Prescaler Control Register 0 to 3 (UTCR0 to UTCR3)
and UART Prescaler Reload Register 0 to 3 (UTRLR0 to
UTRLR3)
UART prescaler control registers 0 to 3 (UTCR0 to UTCR3) are responsible of setting
start-up/halt of the prescaler, forced reset, and selecting clock sources. The UART
prescaler control registers 0 to 3 (UTCR0 to UTCR3) are also responsible of setting the
division rate of the machine clock by combining their lower 3 bits with UART prescaler
reload registers 0 to 3 (UTCR0 to UTCR3).
UART Prescaler Control Register 0 to 3 (UTCR0 to UTCR3) and UART Prescaler Reload
Register 0 to 3 (UTRLR0 to UTRLR3)
The UART operation clock is obtained by dividing the machine clock. Is designed to obtain a certain level
of baud rate for a wide variety of machine cycles using this prescaler. Figure 21.4-7 shows the configuration
of UTCR0 to UTCR3.
Figure 21.4-7 UART Prescaler Control Register 0 to 3 (UTCR0 to UTCR3) and UART Prescaler Reload
UART prescaler control register 0 to 3 (UTCR0 to UTCR3)
UART prescaler reload register 0 to 3 (UTRLR0 to UTRLR3)
R/W : Readable/Writable
: Undefined
[bit 15] MD: Prescaler permission bit
It is an operation permission bit of the prescaler.
0: Prescaler is stop.
1: Prescaler is in operation.
[bit 14] SRST: UART compulsion reset bit
It is an internal reset bit for UART. Forcibly resets UART to initialize. Once initialized, turns to "0"
automatically.
0:State maintenance
1: Forced reset
492
Register 0 to 3 (UTRLR0 to UTRLR3)
bit15 bit14
Address
ch0 : 000025
H
MD SRST CKS
ch1 : 00002B
H
ch2 : 000031
H
R/W R/W
ch3 : 000037
H
Address bit7
ch0 : 000024
H
D7
ch1 : 00002A
H
ch2 : 000030
H
R/W R/W
ch3 : 000036
H
bit13 bit12 bit11 bit10
D10
Reserved
R/W R/W R/W
bit5
bit6 bit4 bit3 bit2
D3
D6 D5 D4 D2
R/W R/W R/W
R/W
bit9
bit8
Initial value
D9 D8 0000-000
R/W R/W
bit1 bit0
Initial value
00000000
D1 D0
R/W R/W
B
B