Execution Cycle Count - Fujitsu F2MC-16LX Hardware Manual

B.5

Execution Cycle Count

The number of cycles required for executing an instruction (the number of execution
cycles) can be obtained by summing the "number of cycles" for each instruction, the
"correction value" that is determined by the condition, and the "number of cycles" of
the program fetch.
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. When fetching an program in memory, such as integrated ROM,
which is connected to a 16-bit bus, program fetch is performed whenever the running instruction crosses
over the word boundary. This will result in increasing the number of execution cycles if data access is
interfered.
When fetching a program in memory connected to an 8-bit bus such as external data bus, program fetch is
performed for each byte of the running instruction. This will result in increasing the number of execution
cycles if data access is interfered. If a general-purpose register, integrated ROM, integrated RAM,
integrated I/O or external data bus is accessed during CPU intermittent operation, the supply of clock to the
CPU pauses by the number of cycles specified by the CG0 and CG1 bits of the low power consumption
mode control register. Therefore, the number of cycles required for executing the instructions for CPU
intermittent operation must be calculated by adding a "correction value" (a value obtained from "the
number of these accesses" × "the number of cycles" in a pause) to "the number of execution cycles" at
usual time.
Appendix B Instruction
629