Fujitsu F2MC-16LX Hardware Manual page 10

Register of µDMAC.......................................................................................................................... 89
3.8.2
3.8.2.1 DMA Descriptor Channel Specification Register (DCSR) ............................................................ 90
3.8.2.2 DMA Status Register (DSRH/DSRL)............................................................................................ 92
3.8.2.3 DMA Stop Status Register (DSSR) .............................................................................................. 93
3.8.2.4 DMA Permission Register (DERH/DERL) .................................................................................... 94
3.8.3 DMA Descriptor Window Register (DDWR)..................................................................................... 95
3.8.3.1 DMA Data Counter (DDCTH/DDCTL) .......................................................................................... 96
3.8.3.2 DMA I/O Register Address Pointer (DIOAH/DIOAL) .................................................................... 97
3.8.3.3 DMA Control Register (DMACS) .................................................................................................. 98
3.8.3.4 DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) ............................................................ 100
Explanation of Operation of µDMAC.............................................................................................. 101
3.8.4
3.9 Exceptions .......................................................................................................................................... 103
3.10 Stack Operation of Interrupt Processing ............................................................................................. 104
3.11 Program Example of Interrupt Processing .......................................................................................... 106
3.12 Delayed Interrupt Generation Module................................................................................................. 110
3.12.1 Operation of Delayed Interrupt Generation Module ....................................................................... 111
CHAPTER 4 RESET ........................................................................................................113
4.1 Outline of Reset .................................................................................................................................. 114
4.2 Reset Factors and Oscillation Stabilization Wait Times...................................................................... 116
4.3 External Reset Pin .............................................................................................................................. 118
4.4 Reset Operation.................................................................................................................................. 119
4.5 Reset Factor Bit .................................................................................................................................. 121
4.6 State of Each Pin at Reset.................................................................................................................. 123
CHAPTER 5 CLOCK........................................................................................................125
5.1 Outline of Clock................................................................................................................................... 126
5.2 Block Diagram of Clock Generation Section....................................................................................... 129
5.3 Clock Select Register (CKSCR).......................................................................................................... 132
5.4 Clock Mode ......................................................................................................................................... 135
5.5 Oscillation Stabilization Wait Time...................................................................................................... 138
5.6 Connection of Oscillator and External Clock....................................................................................... 139
CHAPTER 6 LOW-POWER CONSUMPTION MODE......................................................141
6.1 Outline of Low-Power Consumption Mode ......................................................................................... 142
6.2 Block Diagram of Low-power Consumption Control Circuit ................................................................ 145
6.3 Low-power Consumption Mode Control Register (LPMCR) ............................................................... 147
6.4 CPU Intermittent Operation Mode....................................................................................................... 150
6.5 Standby Mode..................................................................................................................................... 151
6.5.1 Sleep Mode.................................................................................................................................... 152
6.5.2 Timebase Timer Mode ................................................................................................................... 154
6.5.3 Watch Mode................................................................................................................................... 156
6.5.4 Stop Mode ..................................................................................................................................... 158
6.6 State Transition Diagram .................................................................................................................... 160
6.7 State of the Pin during Standby Mode, Hold, and Reset .................................................................... 162
6.8 Precautions when Using Low-power Consumption Mode .................................................................. 172
CHAPTER 7 MODE SETTING .........................................................................................175
7.1 Mode Setting....................................................................................................................................... 176
7.2 Mode Pins (MD2 to MD0) ................................................................................................................... 177
vi