Host Error Status Register (Herr) - Fujitsu F2MC-16LX Hardware Manual

14.4.3

Host Error Status Register (HERR)

The host error status register (HERR) is a register that indicates whether an error
occurs or not when sending or receiving data in host mode.
Host Error Status Register (HERR)
Figure 14.4-3 Bit Configuration of Host Error Status Register (HERR)
Host error status register
Address: 0000C3
H
→
Read/Write
→
Initial value
Reset On/Off at UDCC RST bit →
[bit 15] LSTSOF:SOF execution error
It indicates that an SOF token could not be executed because another token was running when you tried
to execute it in host mode. Please do "0" in the writing to clear "1". To update them, you must set the
RST bit in the UDC control register (UDCC) to "0".
[bit 14] RERR: Receive error
It indicates whether data more than a maximum number of packets set was received in host mode.
When the reception error occurs, TOUT is set in "1".
Please do "0" in the writing to clear "1". To update them, you must set the RST bit in the UDC control
register (UDCC) to "0".
15 14 13
LSTSOF RERR TOUT
(R/W) (R/W) (R/W)
(0) (0) (0)
( ) ( ) (
LSTSOF
0 SOF execution
1 SOF execution error
RERR
0 No receive error
1 The maximum packet reception error
12 11
CRC TGERR
(R/W) (R/W)
(0) (0)
) ( ) ( )
Operation mode
Operation mode
CHAPTER 14 USB Mini-HOST
10 9 8
STUFF HS
(R/W) (R/W)
(0) (11)
( ) ( )
←
bit number
HERR
323