Holding Function - Fujitsu F2MC-16LX Hardware Manual

7.5.3

Holding Function

The operation of the hold function is described in the timing chart.
Operation of Holding Function
If the HDE bit in the EPCR is set to "1", the hold function of the external bus by both the P54/HRQ and the
P55/HAK pins are enabled. When the "H" level is input to the P54/HRQ pin, the pin enters in the hold state
when CPU's instruction ends (for the string instruction, when 1 element data procedure ends), and outputs
the "L" level from the P55/HAK and the following pin enters into the high-impedance state.
Non-multiplex mode
• Address output:A23 to A00
• Data I/O:D15/AD15 to D00/AD00
• Bus control signal: P51/RD,P52/WRL,P53/WRH
Multiplex mode
Address output:A23 to A16
Data I/O:D15/AD15 to D00/AD00
Bus control signal: P51/RD,P52/WRL,P53/WRH
Thus, the device external circuit enables the use of the external bus. If the "L" level is input to the P54/
HRQ pin, the p55/HAK pin becomes the "H" level output and the external pin state is restored, and then the
CPU restarts the operation. In the state of STOP, the holding demand is not accepted.
Non-multiplex Mode
Figure 7.5-7 shows the timing chart of the hold function of the non-multiplex mode in the external data bus
16-bit mode.
CHAPTER 7 MODE SETTING
195