Dma Descriptor Channel Specification Register (Dcsr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPT
3.8.2.1

DMA Descriptor Channel Specification Register (DCSR)

DMA descriptor channel specification register (DCSR) switches the descriptor of each
channel.
The descriptor is set after the channel is specified by this register.
DMA Descriptor Channel Specification Register (DCSR)
00009B
H
R/W : Readable/Writable
[bit 11 to bit 8] DCSRx: Specifies the DMA descriptor channel.
Table 3.8-1 Relation between DCSR and Selector Channel
DCSR3 to DCSR0 Selection channel
0000
B
0001
B
0010
B
0011
B
0100
B
0101
B
0110
B
0111
B
1000
B
1001
B
1010
B
1011
B
1100
B
1101
B
1110
B
1111
B
90
Figure 3.8-2 DMA Descriptor Channel Specification Register
15 14 13
STP
Reserved Reserved Reserved
R/W R/W R/W R/W
0 USB function 1 (End Point 0-IN)
1 USB function 1 (End Point 0-OUT)
2 USB function 2 (End Point 1)*
3 USB function 2 (End Point 2)*
4 USB function 2 (End Point 3)
5 USB function 2 (End Point 4)
6 USB function 2 (End Point 5)
7 Input capture 0,1
8 Input capture 2,3
9 I/O extended serial
10 UART2/3, Reception
11 UART2/3, Transmission
12 UART0/1, Reception
13 UART0/1, Transmission
14 PWC, reload timer 0
15 A/D converter, conversion end, and free run timer
12 11 10 9
DCSR3 DCSR2 DCSR1 DCSR0
R/W R/W R/W
Resource interrupt request
8
DCSR
R/W Initial value 00000000
B