Fujitsu F2MC-16LX Hardware Manual page 511

Transmission Interrupt
When sending data is sent from the serial output data registers 0 to 3 (SODR0 to SODR3) to the sending
shift register, then the sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1". When sending
interrupts are enabled (SSR0 to SSR3: TIE=1), a sending interrupt request is generated.
Interruption of UART, EI
Table 21.5-2 Interruption of UART, EI
Interrupt
Interrupt cause
number
UART3
#35(23
Reception Interrupt
UART3
#33(21
Transmission Interrupt
UART2
#35(23
Reception Interrupt
UART2
#33(21
Transmission Interrupt
UART1
#39(27
Reception Interrupt
UART1
#37(25
Transmission Interrupt
UART0
#39(27
Reception Interrupt
UART0
#37(25
Transmission Interrupt
: Available; with a function that stops EI
: Available
2
UART EI OS Function
UART has the circuit of the EI
occasion of each of the send interrupt and the receive interrupt.
At Transmission/Reception
At the transmission / reception, EI
2
OS, and µDMAC
2 OS, and µDMAC
Interrupt control
register
Register
Address
Name
) 0000BC
ICR12
H H
) 0000BB
ICR11
H H
) 0000BC
ICR12
H H
) 0000BB
ICR11
H H
) 0000BE
ICR14
H H
) 0000BD
ICR13
H H
) 0000BE
ICR14
H H
) 0000BD
ICR13
H H
2
OS by detecting a UART receive error
2
OS correspondence. This allows EI
2
OS is available regardless of the states of any other peripherals.
Vector table address
Low High Bank
FFFF70 FFFF71 FFFF72
H H
FFFF78 FFFF79 FFFF7A
H H
FFFF70 FFFF71 FFFF72
H H
FFFF78 FFFF79 FFFF7A
H H
FFFF60 FFFF61 FFFF62
H H
FFFF68 FFFF69 FFFF6A
H H
FFFF60 FFFF61 FFFF62
H H
FFFF68 FFFF69 FFFF6A
H H
CHAPTER 21 UART
µDMAC
2
Channel
EI OS
number
10
H
11
H
10
H
11
H
12
H
13
H
12
H
13
H
2
OS to start up separately on the
495