Fujitsu F2MC-16LX Hardware Manual page 239

Table 10.2-1 Function of Each Bit of Watchdog Timer Control Register (WDTC)
Bit name
bit 7 PONR
bit 5 WRST
bit 4 ERST
bit 3 SRST
bit 6 Reserved
bit 2 WTE
bit 1 WT1
bit 0 WT0
• Read-only bits that indicate reset factors. When a reset factor occurs, the
relevant bit is set to "1".
• The PONR, WRST, ERST and SRST bits are all cleared to "0" after the
Reset factor bit WDTC register is read.
• The contents of the bits other than the PONR bit are not assured at power-on.
Therefore, when the PONR bit is "1", ignore the contents of the bits other
than the PONR bit.
• The reading value is irregular.
Reserved bit
• Writing does not have the influence in the operation.
• Writing "0", activates the watchdog timer (at the first write after reset) or
Watchdog
clears the 2-bit counter (at the second write after reset).
control bit
• There is no influence in the operation in writing "1".
• This is a bit to select the interval time of the watchdog timer.
• The interval timer when the sub clock mode is selected as the clock mode (the
sub clock display bit (SCM) of clock select register (CKSCR) sets to "0") or
when the watch timer is used as the clock source of watchdog timer
(watchdog timer clock source select bit (WDCS) sets to "0") is different from
Interval time
when the main clock mode or PLL clock mode is selected as the clock mode
select bit
and the WDCS bit of the WTC is set to "1" as shown in Figure 10.2-1
according to the setting of the watch timer control register (WTC).
• The data at the activation of the watchdog timer is valid. Data written after
the activation of the watchdog timer is ignored.
• The WT1 and WT0 bit are only for writing.
CHAPTER 10 WATCHDOG TIMER
Functions
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