Fujitsu F2MC-16LX Hardware Manual page 395

Range of Count at Pulse Width/cycle
Measurable ranges of pulse width/cycle vary depending on the selected combination of division ratios of
count clock and input divider.
Table 15.3-7 shows the measurement range list of machine clock when the clock frequency (called Φ
hereafter) is 24 MHz.
Table 15.3-7 Pulse Width Measurement Range List
Divide ratio
None
4-frequency division
16-frequency division
64-frequency division
256-frequency division
Note: These values enclosed in brackets ( ) indicate the granularity per bit
Interrupt Request Generation
Two following interrupt requests can be generated in the pulse width measurement mode:
Interrupt request by overflow of timer
When an overflow is generated by the count up during the measurement, the overflow flag is set. When the
overflow interrupt request is permitted, an interrupt request occurs.
Interrupt request by measurement termination
When the measurement termination edge is detected, the measurement termination flag (EDIR) in the
PWCSR is set. If the measurement termination interrupt request is permitted, the interrupt request occurs.
The measurement termination flag (EDIR) is automatically cleared as soon as the measured result PWCR is
read.
in CKS1,CKS0=
DIV1 DIV0
00(Φ/4)
0.17 µs to 10.92 ms
- -
(0.25 µs)
0.17 µs to 2.73 ms
0 0
(6.25 µs)
0.17 µs to 683 µs
0 1
(15.6 ns)
0.17 µs to 170 µs
1 0
(3.91 µs)
0.17 µs to 43 µs
1 1
(0.98 µs)
CHAPTER 15 PWC TIMER
in CKS1,CKS0=
01(Φ/16)
0.17 µs to 43.7 ms
(1.6 µs)
0.17 µs to 10.92 ms
(0.4 µs)
0.17 µs to 2.73 ms
(1.6 µs)
0.17 µs to 683 µs
(25 µs)
0.17 µs to 171 µs
(6.25 µs)
in CKS1,CKS0=
10(Φ/32)
0.17 µs to 87.4 ms
(3.2 µs)
0.17 µs to 21.85 ms
(0.8 µs)
0.17 µs to 5.46 ms
(0.2 µs)
0.17 µs to 1.36 ms
(50 ns)
0.17 µs to 341 µs
(12.5 ns)
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