Fujitsu F2MC-16LX Hardware Manual page 175

Notes:
• When handling an interrupt, the CPU usually services the interrupt after executing the instruction
that follows the one specifying the stop mode. When transition to stop mode and acceptance of
an external bus hold request have occurred at the same time, interrupt processing may transit
before executing the next instruction.
• In PLL stop mode, the main clock and PLL multiplier circuit remain stopped. When the CPU
returns from PLL stop mode, therefore, it is necessary to allow for the main clock oscillation
stabilization wait time and PLL clock oscillation stabilization wait time. In this case, the oscillation
stabilization wait time concurrently counts the main clock oscillation stabilization wait time and the
PLL clock oscillation stabilization wait time, according to the value specified in the oscillation
stabilization wait time selection bit (CKSCR; WS1, WS0) of the clock selection register, thus the
CKSCR; WS1, WS0 bit must be set in accordance with the longer oscillation stabilization wait
time. However, as the PLL clock stabilization wait time requires at least 2
the CKSCR; WS1, WS0 bit to "10
Figure 6.5-3 shows the cancellation operation of the stop mode.
RST Pin
Stop mode
Main clock
PLL clock
Sub clock
CPU clock
CPU operation
B
Figure 6.5-3 Cancellation of Stop Mode (External Reset)
CHAPTER 6 LOW-POWER CONSUMPTION MODE
" or "11 ".
B
Oscillation stabilizing wait
suspension
suspension
Reset cancellation
Stop mode cancellation
14
/HCLK, be sure to set
oscillation
Main clock
Processing
Reset sequence
159