Processor Status (Ps) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 2 CPU
2.3.3

Processor Status (PS)

The function of processor status (PS) is explained.
Processor Status (PS)
The processor status (PS) consists of bits to perform the CPU operation and to indicate the CPU status. As
shown in Figure 2.2-6, the upper byte of PS register consists of the register bank pointer (RP) and the
interrupt level mask register (ILM). The RP indicates the start address of register bank while the lower byte
of PS register is the condition code register (CCR) containing the flag which is set or reset by the execution
result or an interrupt occurrence.
Figure 2.3-6 shows the configuration of the processor status (PS).
Condition Code Register (CCR)
Figure 2.3-7 shows the configuration of the condition code register.
Figure 2.3-7 Configuration of the Condition Code Register (CCR)
Initial value
Interrupt enable flag (I)
Interrupts other than software interrupt are enabled and masked when the I flag is "1" and "0", respectively.
The I flag is cleared by the reset.
Stack flag (S)
When the S flag is "0" and "1", the USP and the SSP are valid as a stack manipulation pointer, respectively.
The S flag is set by an interrupt or a reset.
Sticky-bit flag (T)
"1" is set to the T flag when the data contain one or more "1" that has been shifted out from a carry after the
execution of logical right or arithmetic right shift instruction. "0" is set otherwise. When the amount of the
shift is 0, "0" is set in T flag.
Negative flag (N)
The N flag is set and cleared when the MSB of operation result is "1" and any other, respectively.
36
Figure 2.3-6 Configuration of Processor Status (PS)
12
15 13
PS
ILM RP
7 6 5 4
I
S T
×
0 1
7
CCR
3 2 1 0
N V C
Z
×
× × × × : Undefined value
0