Fujitsu F2MC-16LX Hardware Manual page 513

Figure 21.5-1 Timing of Receiving Operation and Set of Flags
Receive data
(Operation mode 0)
Receive data
(Operation mode 1)
Receive data
(Operation mode 2)
*
PE, ORE, FRE
RDEF
* : PE flag cannot be use in mode 1.
PE, FRE flag cannot be used in mode 2.
ST : Start bit
SP : Stop bit
A/D : Address of mode 1 (multiprosessor mode)/Data selection bit
Timing of receiving interrupt generation
When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), any of a receiving data full flag (SSR0 to
SSR3: RDRF), a parity error flag (SSR0 to SSR3: PE), an overrun error flag (SSR0 to SSR3:ORE), and a
framing error flag (SSR0 to SSR3: FRE) is set to "1", then a receiving interrupt request is generated.
ST
D0 D1
ST
D0 D1
D0 D1
CHAPTER 21 UART
D5 D6 D7/P
SP
D7
D6 A/D SP
D6
D4 D5 D7
Receive Interrupt generation
497