Indirect Addressing; B.4 Indirect Addressing - Fujitsu F2MC-16LX Hardware Manual

B.4

Indirect Addressing

In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
Indirect Addressing
Register indirect (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23
are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB)
or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is
used.
Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1
Register indirect with post increment (@RWj+ j=0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand data length (for byte, incremented by 1; for word,
incremented by 2; for long word, incremented by 4).Address bits 16 to 23 are indicated by the data bank
register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register
(USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
If the resultant value of post increment points to the address of the resister specifying the increment, the
incremented value will be referenced subsequently. In this case, if the instruction is a write instruction,
writing by the instruction takes precedence and the register that should have been incremented contains
write data.
Figure B.4-2 Example of Register Indirect with Post Increment (@RWj + j = 0 - 3)
MOVW A, @RW1+
(This instruction reads data by register indirect addressing
and stores it in A.)
Before execution A 0 7 1 6
RW1 D 3 0 F
After execution
A 2 5 3 4
RW1 D 3 0 F
(This instruction reads data by register indirect addressing
with post increment and stores it in A.)
Before execution A 0 7 1 6
RW1 D 3 0 F
After execution
A 2 5 3 4
RW1 D 3 1 1
2 5 3 4
Memory space
DTB 7 8 78D310 F F
H
78D30F E E
H
F F E E
DTB 7 8
2 5 3 4
Memory space
78D310 F F
DTB 7 8
H
78D30F E E
H
F F E E
DTB 7 8
Appendix B Instruction
623