Fujitsu F2MC-16LX Hardware Manual page 546

2
CHAPTER 22 I C INTERFACE
• Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur
When an instruction which generates a start condition by enabling I
(setting the MSS bit in the IBCR register to "1") with the I
This is because, as shown in Figure 22.2-5, when the other master on the I
2
I C disabled (EN bit=0), the I
Figure 22.2-5 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur
SCL pin
SDA pin
EN bit
MSS bit
AL bit
BB bit
INT bit
If a symptom as described above can occur, follow the procedure below for software processing.
1. Execute the instruction that generates a start condition (set the MMS bit to "1").
2. Use, for example, the timer function to wait for the time* for three-bit data transmission at the I
frequency set in the ICCR register.
Example: Time for three-bit data transmission at an I
{1/(100×103)}×3=30 µs
3. Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0", respectively, set
the EN bit in the ICCR register to "0" to initialize I
processing.
A sample flow is given below.
Set the MSS bit in the bus control register (IBCR) to 1.
Wait* for the time for three-bit data transmission at the I
transfer frequency set in the clock control register (ICCR).
530
2
C bus enters the occupied state with no start condition detected (BB bit =0).
The INT bit interrupt does not occur
Start Condition in the ninth clock cycle.
SLAVE ADDRESS
Master mode setting
BB bit=0 and AL bit=1?
YES
Set the EN bit to 0 to initialize I
2
C operation (EN bit=1) is executed
2
C bus occupied by another master.
2
ACK DATA
2
C transfer frequency of 100 kHz
2
C. When the AL and BB bits are not so, perform normal
2
C
NO
to normal process
2
C
C bus starts communication with
Stop Condition
ACK
0
0
2
C transfer