Fujitsu F2MC-16LX Hardware Manual page 509

[bit 13] CKS: clock source selection bit
The clock source is selected.
0: Dedicated baud rate generator
1: External clock
[bit 12] Reserved: reserved bit
It is Reserved bit.
Be sure to set this bit to "0".
[bit 11] Undefined bit
This bit is undefined when it is read. Nothing is affected when it is written.
[bit 10 to bit 0] D10 to D0:Fundamental period set bit
<Asynchronous mode>
Two cycles of the serial clock worth of a cycle is decided.
UART is responsible for dividing the serial clock into 8 pieces, and baud rate is as follows.
BAUD RATES= φ/4n(bps)
φ:Machine clock n:D10 to D0 (fundamental period set bit)
However, please set neither n=1 or 2 nor 3.
<Clock synchronous mode>
BAUD RATES = 2φ/n (bpc)
φ : Machine clock n : D10 to D0 (fundamental period set bit)
However, please set n to "00
Notes:
• Setting "01
cycle set bit generates the serial clock whose duty ratio is different. So set D1 and D0 (bit 1 and 0
of UTRLR0 to UTRLR3) to "00
• Please access UTCR0 to UTCR3 and UTRLR0 to UTRLR3 by word move operation.
• Halt the operation of the prescaler (MD=0 and CKS=0) before you switch the clock source.
• When the external selection mode is selected and if you need to modify the reload value, halt the
operation of the prescaler (MD=0 and CKS=0) before you change to your reload value.
• Please set neither reload value n=1, 2 nor 3.
", in case of n ≥ 16 (D1, D0).
B
", "10 ", and "11 " to D1 and D0 (bit 1 and 0 of UTRLR0 to UTRLR3) of the basic
B B B
" when in the clock synchronization mode.
B
CHAPTER 21 UART
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