Fujitsu F2MC-16LX Hardware Manual page 243

Figure 10.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer
[Block diagram of Watchdog timer]
Clock selector
[Minimum interval time] When clear WTE bit immiediately before rising of count clock
Counter clear
Count clock a
2 divided value b
2 divided value c
Count enable
Reset signal d
[Maximum interval time] When clear WTE bit immiediately after rising of count clock
Counter clear
Count clock a
2 divided value b
2 divided value c
Count enable
Reset signal d
WTE bit clear
2-bit counter
a
2 divided
circuit
Count enable
output circuit
WTE bit
Count start
(Count clock cycle/2)
7
WTE bit clear
Count start
7 (Count clock cycle/2)
CHAPTER 10 WATCHDOG TIMER
b c
2 divided
Reset circuit
circuit
Count enable and clear
Watchdog reset generation
Watchdog reset generation
d
Reset
signal
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