Fujitsu F2MC-16LX Hardware Manual page 195

Set Bit of Bus Mode (M1,M0)
The M1and M0 bits specify the operation mode after the reset sequence.
Table 7.3-2 shows the content of the M1, M0 bit setting.
Table 7.3-2 Content of M1 and M0 Bit Setting
M1
0
0
1
1
Relation between Access Area and Physical Address
Figure 7.3-2 shows the relation between the access area and the physical address.
Figure 7.3-2 Relation between Access Area and Physical Address
FFFFFF
Address#1
00FFFF
Address#2
007900
Address#3
000100
0000FB
000000
Note:
The "address #X" is determined by each family. Please refer to "Appendix A memory map" for
details.
M0
0 Single-chip mode
1 Internal ROM external bus modes
0 External ROM external bus modes
1 (Setting prohibited)
Single chip Internal ROM external bus
(with ROM mirrorring function) (with ROM mirrorring function)
H
ROM area
H
Image of
FF bank
in ROM area
Extended
I/O area
H
RAM Register
H
H
Peripheral
H
: Internal
Function
External ROM bus
ROM area
Image of
FF bank
in ROM area
Extended Extended
I/O area I/O area
RAM
Register
RAM
Peripheral Peripheral
: External
CHAPTER 7 MODE SETTING
Register
: No access
179