Operation Of Internal Clock Mode (Single Shot Mode) - Fujitsu F2MC-16LX Hardware Manual

16.3.3

Operation of Internal Clock Mode (Single Shot Mode)

It is synchronized with the internal count clock, the 16-bit counter performs the count
down, and the counter underflow generates the CPU interrupt request. Also the TOT pin
can output rectangular waveforms indicating that counting is going on.
Internal Clock Mode (Single Shot Mode)
When the count operation is permitted (CNTE = 1 for TMCSR) and the timer is stared by the software
trigger bit (TRG of TMCSR) or an external trigger, the count operation is started. When the count
permission bit and the software trigger bit are simultaneously set to "1", the count is started at the same
time of the count permission. When the counter value underflows ("0000
in the state of "FFFF
interrupt request permission bit (INTE) is set to "1", the interrupt request occurs.
In addition, the rectangular waveform indicating the count operation can be output from the TOT terminal.
Operation of Software trigger
When "1" is written to TRG bit of timer control status register (TMCSR), the counter is started.
Figure 16.3-7 shows the software trigger operation in the one-shot mode.
Figure 16.3-7 Count Operation in One-shot Mode (Software Trigger Operation)
Count clock
Counter
Data load
signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T: Machine cycle
*: It takes 1T time from trigger input to loading of reload data.
Operation of External trigger
When a valid edge (rising edge, falling edge, or both edges can be selected) is input to the TIN pin, the
counter is started.
Figure 16.3-8 shows the external trigger operation in the one-shot mode.
". At this moment, if the underflow interrupt request flag bit (UF) is set to "1" and the
H
−1
Reload 0000 FFFF
H
data
Start trigger input wait
−1
Reload
H
data
CHAPTER 16 16-BIT RELOAD TIMER
" → "FFFF
"), the counter stops
H H
0000 FFFF
H H
399