Output Compare Timing - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 12 16-BIT I/O TIMER
12.3.5

Output Compare Timing

The output compare indicates that a compare match signal that is generated when the
free-run timer match the value set in the compare registers can reverse the output value
and raise an interrupt. The output inverse timing when a comparing match is detected is
in sync with the counter timing.
Interrupt Timing
Figure 12.3-8 shows the output compare interrupt timing.
φ
Counter value
Compare register
value
Compare match
Compare match
Change Timing for Output Pin
Figure 12.3-9 shows the change timing for the output pin of the output compare.
Figure 12.3-9 Change Timing for Output Pin of Output Compare
Counter value
Compare register
Compare match
Output pin
Note:
If you rewrite compare registers, you must rewrite them in a compare interrupt routine or in the state
of disabled compare operation to ensure that compare-match operation and write operation never
occur at the same time.
262
Figure 12.3-8 Output Compare Interrupt Timing
N
value
signal
N
N
N+1
N
N+1
N
N+1