Fujitsu F2MC-16LX Hardware Manual page 697

16-bit microcontroller mb90330 series
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LQFP-120
Package Dimension (LQFP-120)
Pin Assignment (LQFP-120)
M
M0
Set Bit of Bus Mode (M1,M0)
M1
Set Bit of Bus Mode (M1,M0)
Machine Clock
................................................... 136
Machine Clock
Main Clock Mode
Main Clock Mode, PLL Clock Mode,
Sub Clock Mode
Master/Slave Mode
Master/Slave Mode Communication Function
Maximum Cycle
Count Clock and Maximum Cycle
MB90330 Series
Block Diagram of the MB90330 Series
Feature of MB90330 Series
MD
Setting of Mode Pins (MD2 to MD0)
Measurement
Data of Measurement Result
Measurement Mode and Counter Operation
Operation Flow of Pulse Width Measurement
Memory Map
2
....................................... 556
E
PROM Memory Map
............................................... 27, 598
Memory Map
System Configuration and E
.................................................... 556
Map
Memory Space
Arrangement of Multi Byte Length Data in Memory
.................................................... 30
Space
µDMAC
Interrupt of Timebase Timer and EI
µDMAC Function
................................................. 88
µDMAC Register List
............................................ 89
µDMAC Use Procedure
....................................... 102
Mini-HOST
Feature of USB Mini-HOST
Register of USB Mini-HOST
Setting of Mini-HOST Function
UART Block Diagram of USB Mini-HOST
Minimum Connection
Example of Minimum Connection to Flash Microcomputer
Programmer (when Using User Power)
Mode Data
........................................................ 178
Mode Data
Relation between Mode Pin and Mode Data
(Recommended Example)
State of Pins after Mode Data Read
Mode Fetch
....................................................... 120
Mode Fetch
................................ 8
................................... 10
............................... 179
............................... 179
.................................... 135
........... 514
.......................... 374
........................ 7
....................................... 2
...................... 177
................................. 376
.............. 377
........... 380
2
PROM Memory
2
OS, µDMAC
...... 212
.................................. 310
................................. 313
............................. 337
.............. 312
....... 595
........................ 180
......................... 123
Mode Pin
..........................................................119
Mode Pin
Relation between Mode Pin and Mode Data
(Recommended Example)
Mode Pins
Setting of Mode Pins (MD2 to MD0)
Mode Setting
......................................................176
Mode Setting
Mode Type
........................................................188
Mode Type
Multi Byte Length Data
Arrangement of Multi Byte Length Data in Memory
....................................................30
Space
Multi Byte Length Data Access
Multiple Interrupts
Example of Multiple Interrupts
.................................................68
Multiple Interrupts
Multiple Mode
....................................................196
Multiple Mode
Multiplex 16-bit External Bus
Pin State in External Bus 16-bit Data Bus and Multiplex
16-bit External Bus Mode
Multiplex 8-bit External Bus
Pin State in External Bus 8-bit Data Bus and Multiplex 8-bit
External Bus Mode
Multiplex Mode
External 16-Bit Bus Mode (External Data Bus 16-Bit/
Multiplex Mode)
Multiplication Rate
Selection of PLL Clock Multiplication Rate
N
NCC
Flag Change Suppression Prefix (NCC)
Non-multiplex 16-bit External Bus
Pin State in External Bus 16-bit Data Bus and Non-multiplex
16-bit External Bus Mode
Non-multiplex 8-bit External Bus
Pin State in External Bus 8-bit Data Bus and Non-multiplex
8-bit External Bus Mode
Non-multiplex Mode
............................................195
Non-multiplex Mode
Notes
Notes on Accessing the Low-power Consumption made
Control Register (LPMCR)
NULL Transfer
..........................................308
NULL Transfer Mode
O
OCCP
Output Compare Registers (OCCP0 to OCCP3)
OCS
Output Compare Control Registers
(OCS0 to OCS3)
INDEX
........................180
.......................177
................................31
.................................69
........................164
.................................166
....................................191
..............136
......................44
........................168
..........................170
.......................174
.........248
....................................249
681

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