Fujitsu F2MC-16LX Hardware Manual page 505

Table 21.4-3 Description of Each Bit of the Serial Status Registers 0 to 3 (SSR0 to SSR3)
Bit name
RIE:
Reception
bit 9
interrupt request
enable bit
TIE:
Transmission
bit 8
interrupt request
enable bit
• Enable or disable receive data.
• When set to "1": If receiving data is loaded to the serial input data registers 0 to 3 (SSR0
to SSR3: RDRF=1). Or if an receiving error occurs (SSR0 to SSR3:
PE=1, or ORE=1, or FRE=1), then a receiving interrupt request is
generated.
• Enable or disable send interrupt.
• When set to "1": If the data written to the serial output data registers 0 to 3 is sent to the
sending shift register (SSR0 to SSR3: TDRE=1), then a sending
interrupt request is generated.
Functions
CHAPTER 21 UART
489