Host Address Register (Hadr) - Fujitsu F2MC-16LX Hardware Manual

14.4.7

Host Address Register (HADR)

The host address register (HADR) is a register used for an address field when a token is
sent.
Host Address Register (HADR)
Figure 14.4-7 Bit Configuration of Host address Register (HADR)
Host address register
Address: 0000C9
H
→
Read/Write
→
Initial value
Reset On/Off at UDCC RST bit →
[bit 15] Reserved
It is reserved bit. The reading is irregular. The writing does not influence the operation.
[bit 14 to bit 8] Address: Address
The address of the token is set. It is not initialized with the RST bit in the UDC control register
(UDCC). To update them, you must set the RST bit in the UDC control register (UDCC) to "0".
15 14 13
Reserved
(-)
(x)
(-)
12 11 10
Address
(R/W)
(0000000 )
B
( )
CHAPTER 14 USB Mini-HOST
←
9 8
bit number
HADR
331