Fujitsu F2MC-16LX Hardware Manual page 702

INDEX
SSR
Serial Status Register 0 to 3 (SSR0 to SSR3)
Stabilization
Sub Clock Oscillation Stabilization Delay Time
.............................................. 236
Function
Stack Area
.........................................................105
Stack Area
Stack Operation
Stack Operation at the Start of Interrupt Processing
Stack Operation when Interrupt Processing Returns
Standby Mode
Cancellation of Standby Mode by Interrupt
Operation Status in Standby Mode
.................................................... 143
Standby Mode
Transition to Standby Mode and Interrupt
Start Condition
...................................................536
Start Condition
Startup
......................................... 371
Operation after Startup
Startup and Stop of Timer/Pulse Width
........................................ 371
Measurement
State
Read/Reset State in Flash Memory
State Transition
State Transition of Data Polling Flag (DQ7)
State Transition Diagram
State Transition Diagram
Status Register
EP1 to EP5 Status Register (EP1S to EP5S)
Extended Intelligent I/O Service (EI
Register (ISCS)
Stop
Startup and Stop of Timer/Pulse Width
........................................ 371
Measurement
................................................................372
Stops
Stop Condition
...................................................536
Stop Condition
Stop Mode
Cancellation of Stop Modes
....................................... 158
Transition to Stop Mode
STP
Priority Level of STP,SLP,and TMD Bit
Sub Clock Mode
Main Clock Mode, PLL Clock Mode,
Sub Clock Mode
Sub Clock Oscillation
Sub Clock Oscillation Stabilization Delay Time
.............................................. 236
Function
Suppression
Hardware Interrupt Suppression
Suspend Operation
.............................................. 349
Suspend Operation
Suspend Processing
............................................. 302
Suspend Processing
Suspension
Flash Memory Sector Erase Suspension
686
............. 487
..... 104
.... 104
............... 172
.......................... 151
................. 172
.......................... 578
.............. 572
......................................160
.............. 291
2
OS) Status
....................................... 79
................................... 158
.................. 149
.................................... 135
............................... 62
...................584
Symbol
Description of Instruction Presentation Items and
.............................................. 633
Symbols
Synchronous Mode
Operation in Synchronous Mode
(Operation Mode 2)
System Configuration
System Configuration and E
.................................................... 556
Map
System Stack Pointer
User Stack Pointer (USP) and
System Stack Pointer (SSP)
T
Taking Timing
Example of Taking Timing of Input Capture
TBTC
Timebase Timer Control Register (TBTC)
TCCS
Timer Control Status Register (TCCS)
TCDT
Timer Counter Data Register (TCDT)
Time Stamp Register
Time Stamp Register (TMSP)
Timebase Timer
Block Diagram of Timebase Timer
Interrupt of Timebase Timer
Interrupt of Timebase Timer and EI
Operation of Interval Timer Function
(Timebase Timer)
Operations of Timebase Timer
Precautions when Using Timebase Timer
Program Example of Timebase Timer
Timebase Timer Control Register
Timebase Timer Control Register (TBTC)
Timebase Timer Mode
Cancellation of Timebase Timer Modes
Transition to Timebase Timer Mode
Timer
Operation Flow of Timer
Startup and Stop of Timer/Pulse Width
........................................ 371
Measurement
Timer Control Status Register
Timer Control Status Register (TCCS)
Timer Control Status Register 0 to 2
(TMCSR0 to TMCSR2)
Timer Counter Data Register
Timer Counter Data Register (TCDT)
Timer Cycle
...................................................... 374
Timer Cycle
Timer Register
16-bit Timer Register 0 to 2 (TMR0 to TMR2)
16-bit Timer Register 0 to 2 (TMR0 to TMR2)/
16-bit Reload Register 0 to 2
(TMRLR0 to TMRLR2)
................................ 509
2
PROM Memory
....................... 35
............. 260
................ 210
.................... 243
..................... 243
................................ 279
......................... 208
.................................. 212
2 OS, µDMAC
...... 212
.................................. 213
............................... 216
................. 215
..................... 217
................ 210
................... 155
....................... 154
...................................... 375
.................... 243
.......................... 389
..................... 243
.......... 393
.......................... 393