Fujitsu F2MC-16LX Hardware Manual page 422

CHAPTER 17 8/16-BIT PPG TIMER
Figure 17.1-2 Block Diagram of 8/16-bit PPG Timer (ch1/ch3/ch5)
Timebase counter output:
divided by 512 of Main clock
406
Peripheral clock 16 division
Peripheral clock
8 division
Peripheral clock
4 division
Peripheral clock
2 division
Peripheral clock
PCNT (Down counter)
L/H
Count clock
selection
L/H selection
PRLL
PRLL
PPG1/PPG3/PPG5
Output enabled
PPG1/PPG3/PPG5
Output latch
PEN1
PUF1
PRLBH
PPGC1/PPGC3/PPGC5
(Operation mode ontrol)
PPG1/PPG3/PPG5
A/D converter
(only PPG1)
S
R Q
IRQ
PIE1
"L" data bus
"H" data bus