Uart Interrupt - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 21 UART
21.5

UART Interrupt

The UART support reception and transmission interrupts, capable of generating an
interrupt request in the following conditions:
• Where the receiving data is set to the serial input data registers 0 to 3 (SIDR0 to
SIDR3), or an receiving error has occurred.
• When data to transmit is transferred from serial output data register 0 to 3 (SODR0 to
SODR3) to the transmission shift register.
Also, support for each extended intelligent I/O service (EI
UART Interrupt
Table 21.5-1 shows the interrupt control bit and interrupt factor of UART.
Table 21.5-1 Interrupt Control Bit of UART and Interruption Factor
Transmission/
Interrupt
Reception
flag bit
RDRF
ORE
Reception
FRE
PE
Transmission TDRE
: Using bit
: Unused bit
Reception Interrupt
When receiving interrupts are enabled (SSR0 to SSR3: RIE=1) and if either completion of data reception
(SSR0 to SSR3: RDRF=1), an overrun error (SSR0 to SSR3: ORE=1), a framing error (SSR0 to SSR3:
FRE=1), or a parity error (SSR0 to SSR3: PE=1) occurs, then an receiving interrupt request is generated.
When the receiving data full flag (SSR0 to SSR3: RDRF) reads the serial input data registers 0 to "3"
(SIDR0 to SIDR3: RDRF), it is automatically cleared to "0". Each reception error flag (SSR0 to SSR3: PE,
ORE, FRE) is cleared to "0" when "0" is written to the reception error flag clear bit (SCR0 to SCR3: REC).
In the case that any receiving error (a parity error, an overrun error, a framing error) occurs, handle such
error where necessary, and then write "0" in the receiving error flag clear bit (SCR0 to SCR3: REC) to clear
each of the receiving error flags.
494
Serial Status Register 0 to 3 (SSR0 to SSR3)
Operating mode
Interrupt cause
0 1 2
Load receive data to the
buffer (SIDR0 to
SIDR3)
Generating overrun
error
Generating framing
error
Generating parity error
Transmission buffer
(SODR0 to SODR3) is
empty.
2
OS), µDMAC.
Interruption
permission Clear Interrupt flag
bit
• Reading receive data
• Reset
• Writing "0" to the
RIE
reception error flag
clear bit (SSR0 to
SSR3: REC)
• Reset
• Writing transmit data
TIE
• Reset