Ep0I Status Register (Ep0Is) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 USB FUNCTION
13.3.7

EP0I Status Register (EP0IS)

The EP0I status register (EP0IS) displays status related to transfer toward In for
EndPoint0.
EP0I Status Register (EP0IS)
Figure 13.3-9 shows the bit configuration of the EP0IS register (EP0IS).
Address bit 7
0000E2 Reserved
H
15
Address bit
0000E3 BFINI
H
1
1
R/W
The function of each bit in the EP0I status register (EP0IS) is described in the following.
[bit 15] BFINI: Transmission buffer initialization bit
The forwarding data transmission buffer is initialized. The BFINI bit is automatically set by setting the
RST bit in the UDC control register (UDCC). Consequently, when the reset operation has been
performed with the RST bit, clear the RST bit before clearing the BFINI bit.
BFINI
0
1
Note:
The initialization of the BFINI bit initializes a buffer and the DRQI bit. You must initialize the buffer
when you have set the STAL bit if necessary after you ensure that the DRQI or DRQO bit is set and
there is no access from the HOST.
[bit 14] DRQIIE: Transmit data interrupt enable bit
It allows an interrupt due to the interrupt factor for the EP0I status register "DRQI" to be generated.
DRQIIE
0
1
286
Figure 13.3-9 EP0I Status Register (EP0IS)
6 5 4
Reserved Reserved Reserved
14 13 12
DRQIIE Reserved Reserved
0
Irrelevance
R/W
Cancelling Initialization
Initialization of transmission buffer
Interrupt disabled by DRQI factor
Interruption permission by DRQI factor
3 2 1
Reserved Reserved Reserved
11 10 9
Reserved DRQI Reserved
1
1
R/W
Operating mode
Operating mode
0
Reserved EP0I status register
8
Reserved
←
Initial value
←
BFINI Reset
←
Access