Configuration Of Timebase Timer - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 9 TIMEBASE TIMER
9.2

Configuration of Timebase Timer

The timebase timer consists of the following four blocks.
• Timebase timer counter
• Counter clear circuit
• Interval timer selector
• Timebase timer control register (TBTC)
Block Diagram of Timebase Timer
Figure 9.2-1 shows the block diagram of the timebase timer.
Timebase timer counter
2 division
×
of HCLK
Power-on reset
Stop mode start
CKSCR : MCS = 1
CKSCR : SCS = 0
Timebase timer control register(TBTC)
Timebase timer interrupt signal
Undefined
OF
Overflow
Oscillation clock
HCLK
Switch Machine clock to PLL clock from Main clock or Sub clock
* 1
* 2 Switch Machine clock to PLL clock from Sub clock
Timebase timer counter
This is an 18-bit up-counter whose count clock is two-division clock of oscillation clock (HCLK).
208
Figure 9.2-1 Block Diagram of Timebase Timer
to PPG timer
× ×
×
1 2
3
2 2
2
Counter
clear
1
0 *
circuit
2
1 *
Reserved
× ×
× × ×
8 9
10 11 12
2 2 2
2 2
OF
OF
Interval timer
selector
TBOF clear
TBIE TBOF TBR TBC1 TBC0
to Watchdog
timer
× × × ×
×
15 16 17
13 14
2 2 2
2 2
OF
OF
to Oscillation
stabilization wait
time selector
in Clock control
unit
TBOF
set
18
2