Fujitsu F2MC-16LX Hardware Manual page 507

Serial Output Data Register 0 to 3 (SODR0 to SODR3)
Figure 21.4-6 shows the bit configuration of serial output data register.
Figure 21.4-6 Serial Output Data Register 0 to 3 (SODR0 to SODR3)
W : Write only
X : Indeterminate
The serial output data register 0 to 3 (SODR0 to SODR3) is a data buffer register for transmitting serial
data.
• When sending operation is allowed (SCR0 to SCR3: TXE=1), and if the sending data is written to the
serial output data registers 0 to 3 (SODR0 to SODR3), the sending data is transferred to the sending shift
register to be converted into the serial data and is sent out from the serial data output pins (SOT0 to SOT
3 pins).
• When the data length is seven bits, the data in upper one bit (SODR0 to SODR3:D7) is invalid.
• The sending data empty flag (SSR0 to SSR3: TDRE) is cleared to "0" as soon as sending data is written
into the serial output data registers 0 to 3 (SODR0 to SODR3).
• The sending data empty flag (SSR0 to SSR3: TDRE) is set to "1" as soon as transmission to the sending
shift register completes.
• If the sending data empty flag (SSR0 to SSR3: TDRE) is set to "1", the next sending data can be written
in. When sending interrupts are enabled, a sending interrupt is generated. Write the subsequent sending
data in the state that the sending data empty flag (SSR0 to SSR3: TDRE) is "1".
Note:
Serial output data registers are write-only, while serial input data registers are read-only. Both of the
registers are located in the same address, so the writing values and reading values are different.
Instructions, such as the INC/DEC instruction, which provide the read modify write (RMW) operation,
cannot be used.
Address
bit7 bit6
ch0 : 000022
H
D7
ch1 : 000028
H
ch2 : 00002E
H
W
ch3 : 000034
H
bit5 bit4 bit3 bit2
D6 D5 D4 D3 D2
W W W
W W
CHAPTER 21 UART
bit1
bit0
Initial value
D1 D0
XXXXXXXX
B
W W
491