Fujitsu F2MC-16LX Hardware Manual page 479

Table 20.2-2 Example of Settings of the Communication Prescaler (SDCR)
Div
MD DIV3
1 1 0
2 1 0
4 1 0
8 1 0
Initialized to "000 " by reset. Rewriting under forwarding is a interdiction.
B
Shift clock includes five alternatives of internal shift clock and one alternative of external shift clock. The
external shifts. Please set neither "110
Providing shift operation for each instruction is also possible by defining SCOE=0 on clock selection and
operating the port sharing SCK pin.
[bit 12] SIE: Serial I/0 Interrupt Enable (enabling serial I/O interrupt)
Serial I/O interrupt request is controlled as shown in the table below.
SIE
0 Interrupt disabled [Initial value]
1 Serial I/O interrupt enabled
• This bit is initialized to "0" at reset.
• This bit can be read and written.
[bit 11] SIR: Serial I/0 Interrupt Request (serial I/O interrupt request)
On completion of the serial data transfer, this bit is set to "1". And when this bit turns to "1" on interrupt
enabled (SIE= "1"), an interrupt request to the CPU occurs. A clear condition is different according to
the MODE bit.
• When MODE bit is "0", it is cleared by writing "0" to SIR bit.
• When MODE bit is "1", it is cleared by writing to or reading SDR bit.
• Regardless of values of MODE bit, it is cleared by resetting or writing "1" to STOP bit.
• It is not significant to write "1".
• On reading read/modify/write instructions, "1" is read in all cases.
[bit 10] BUSY (forwarding status display)
This bit indicates whether serial transfer is running or not.
BUSY
0 Stop or serial data register R/W standby [Initial value]
1 State of serial transfer
• This bit is initialized to "0" at reset.
• This bit can only be read.
CHAPTER 20 EXTENDED I/O SERIAL INTERFACE
(Machine clock)
DIV2 DIV1
0 0
0 0
0 1
1 1
" nor "111 " to SMD2, SMD1, and SMD0.
B B
Operation
Operation
Machine cycle
(Recommended Setting)
DIV0
0 3 MHz
1 6 MHz
1 12 MHz
1 24 MHz
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