Fujitsu F2MC-16LX Hardware Manual page 269

List of Register of Input Capture
Figure 12.2-14 lists input capture registers.
15
ch0:007911
H
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
ch1:007913
H
R
ch2:007915
H
ch3:007917
H
7
ch0:007910
H
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
ch1:007912
H
ch2:007914
R
H
ch3:007916
H
15
000053
H
ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20
R/W R/W
7
000052
H
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
R/W R/W
Input Capture Data Registers (IPCP0 to IPCP3)
Figure 12.2-15 shows the bit configurations of the input capture data registers (IPCP0 to IPCP3).
Figure 12.2-15 Bit Configurations of Input Capture Data Register (IPCP0 to IPCP3)
15
ch0:007911
H
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
ch1:007913
H
R
ch2:007915
H
ch3:007917
H
7
ch0:007910
H
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
ch1:007912
H
ch2:007914 R
H
ch3:007916
H
The input capture data registers (IPCP0 to IPCP3) are registers that hold a value of the 16-bit free-run timer
when the valid edges of waveforms input from their corresponding external pins are detected.
Please access the IPCP0 to IPCP3 register the word. The IPCP0 to IPCP3 registers are not permitted to
write.
Control Status Registers (ICS01,ICS23)
Figure 12.2-16 shows the bit configurations of the control status registers (ICS01 and ICS23).
Figure 12.2-14 List of Register of Input Capture
14 13 12 11
R R R R
6 5 4 3
R R R R
14 13 12 11
R/W R/W R/W
6 5 4 3
R/W R/W R/W
14 13 12 11
R R R R
6 5 4 3
R R R R
10 9 8
IPCP0 to IPCP3
Input capture data register upper
Initial value
R R R
2 1 0
IPCP0 to IPCP3
Input capture data register lower
Initial value
R R R
ICS23
10 9 8
Input capture
control status register 23
Initial value
R/W R/W R/W
ICS01
2 1 0
Input capture
control status register 01
Initial value
R/W R/W R/W
10 9 8
IPCP0 to IPCP3
Input capture data register upper
Initial value
R R R
2 1 0
IPCP0 to IPCP3
Input capture data register lower
Initial value
R R R
CHAPTER 12 16-BIT I/O TIMER
XXXXXXXX
B
XXXXXXXX
B
00000000
B
00000000
B
XXXXXXXX
B
XXXXXXXX
B
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