Fujitsu F2MC-16LX Hardware Manual page 46

CHAPTER 2 CPU
FFFFFF
H
FF0000
H
B3FFFF
H
B30000
H
92FFFF
H
920000
H
68FFFF
H
680000
H
4BFFFF
H
4B0000
H
000000
H
Arrangement of Multi Byte Length Data in Memory Space
Figure 2.2-5 shows the configuration of the multi byte length data in the memory. The lower 8-bit of data
items are stored at the address n and the rest of them are stored at the addresses n + 1, n + 2, and n + 3 in
this description order.
Figure 2.2-5 Example of arrangement of Multi Byte Length Data in Memory
H
01010101
11001100
11111111
00000000
L
Data is written in the memory from the lowest address in ascending order. Therefore, the lower 16-bit of
32-bit long data item are first transferred followed by the upper 16-bit transfer. In addition, if the reset
signal is input immediately after writing the lower bits, the upper bits may sometime not be written.
30
Figure 2.2-4 Physical address of Each Space
Program space
Additional space
User stack space
Data space
System stack space
PCB (Program bank register)
FF
H
ADB (Additional data bank register)
B3
H
USB (User stack bank register)
92
H
DTB (Data bank register)
68
H
SSB (System stack bank register)
4B
H
MSB
01010101 11001100
LSB
00000000
11111111