Fujitsu F2MC-16LX Hardware Manual page 308

16-bit microcontroller mb90330 series

Hide thumbs Also See for F2MC-16LX:

Table of Contents

CHAPTER 13 USB FUNCTION

[bit 15] BFINI: Transmission/receive buffer initialization bit

The transmission and reception buffer of the forwarding data is initialized. The BFINI bit is

automatically set by setting the RST bit in the UDC control register (UDCC). Consequently, when the

reset operation has been performed with the RST bit, clear the RST bit before clearing the BFINI bit.

The transmission/receive buffer for EP1 to EP5 has a configuration of double buffers and

initialization by the BFINI bit initializes the double buffers at once and also initializes the DRQ and

SPK bits. You must initialize the buffers when you have set the STAL bit after you ensure that the

DRQ bit is set and the BUSY bit shows no access from the HOST.

[bit 14] DRQIE: Packet forwarding interruption permission bit

It allows an interrupt due to the interrupt factor for the EP1 to EP5 status register "DRQ" to be

If you use the automatic buffer transfer mode (DMAE=1), you must enable the settings of DMA and

transfer before enabling the DRQIE bit.

[bit 13] SPKIE: Short packet interruption permission bit

It allows an interrupt due to the interrupt factor for the EP1 to EP5 status register "SPK" to be

[bit 12] Reserved bit

This bit is reserved bit. Writing has no effect on the operation. Reading is indeterminate.

Cancelling Initialization

Initialization of transmitting and receiving buffer

Interrupt disabled by DRQ factor

Interruption permission by DRQ factor

Interrupt disabled by SPK factor

Interruption permission by SPK factor

Operating mode