Fujitsu F2MC-16LX Hardware Manual page 693

Procedure for Use of Extended Intelligent I/O Service
2
................................................. 82
(EI OS)
2
........................................ 495
UART EI OS Function
EIRR
DTP/Interruption Factor Register (EIRR: External Interrupt
Request Register)
ELVR
Request Level Setting Register
(ELVR: External Level Register)
End Timing
Automatic Algorithm End Timing
.............................................. 348
Packet End Timing
ENIR
DTP/interruption Permission Register (ENIR: Enable
Interrupt Request Register)
EOF Setting Register
EOF Setting Register (HEOF)
EP
EP0 Control Register (EP0C)
EP0 to EP5 Data Register (EP0DT to EP5DT)
EP1 to EP5 Control Register (EP1C to EP5C)
EP1 to EP5 Status Register (EP1S to EP5S)
EP0DT
EP0 to EP5 Data Register (EP0DT to EP5DT)
EP0I Status Register
EP0I Status Register (EP0IS)
EP0IS
EP0I Status Register (EP0IS)
EP0O Status Register
EP0O Status Register (EP0OS)
EP0OS
EP0O Status Register (EP0OS)
EP1S
EP1 to EP5 Status Register (EP1S to EP5S)
EPCR
Bus Control Signal Selection Register (EPCR)
Equipment
Condition of Peripheral Equipment Connected
............................................... 427
Outside
Erase
Erasing All Data from Flash Memory (Chip Erase)
Erase of Flash Memory
Write/Erase of Flash Memory
Erasing
Erasing Any Data in Flash Memory
(Sector Erasing)
Erasing All Data
Erasing All Data from Flash Memory (Chip Erase)
Erasing Any Data
Erasing Any Data in Flash Memory
(Sector Erasing)
Error Status
....................................................... 347
Error Status
Event Count
.............................................. 401
Event Count Mode
Event Count Mode (External Clock Mode)
.................................. 424
............... 424
.......................... 568
...................... 423
............................... 332
................................ 274
........... 295
........... 276
.............. 291
........... 295
................................. 286
................................. 286
.............................. 288
.............................. 288
.............. 291
.......... 186
..... 581
................................ 577
.................................... 582
..... 581
.................................... 582
............... 385
Execution Cycle
Calculating the Execution Cycle Count
.........................................629
Execution Cycle Count
Extended I/O Serial Interface
Block Diagram in Extended I/O Serial Interface
Interruption Function of Extended I/O Serial
...............................................474
Interface
List of Register in Extended I/O Serial Interface
Outline of Extended I/O Serial Interface
Outline of Operation of Extended I/O Serial
...............................................468
Interface
Extended Intelligent I/O Service
Configuration of Extended Intelligent I/O Service
2
(EI OS) Descriptor (ISD)
Extended Intelligent I/O Service (EI
Extended Intelligent I/O Service (EI
Time (Time for One Transfer)
Extended Intelligent I/O Service (EI
Register (ISCS)
Operation of Extended Intelligent I/O Service
2
............................................75, 81
(EI OS)
Procedure for Use of Extended Intelligent I/O Service
2
..................................................82
(EI OS)
External 16-Bit Bus
External 16-Bit Bus Mode (External Data Bus 16-Bit/
Multiplex Mode)
External Address Output Control Register
External Address Output Control Register
...............................................185
(HACR)
External Bus
Pin State in External Bus 16-bit Data Bus and Multiplex
16-bit External Bus Mode
Pin State in External Bus 16-bit Data Bus and Non-multiplex
16-bit External Bus Mode
Pin State in External Bus 8-bit Data Bus and Multiplex 8-bit
External Bus Mode
Pin State in External Bus 8-bit Data Bus and Non-multiplex
8-bit External Bus Mode
External Bus 16-bit Data Bus
Pin State in External Bus 16-bit Data Bus and Non-multiplex
16-bit External Bus Mode
External Clock
Baud Rate of the External Clock
(One-to-one Mode)
Baud Rate of the External Clock Using the Dedicated
Baud Rate Generator
Connection of Oscillator and External Clock
Event Count Mode (External Clock Mode)
External Data Bus
External 16-Bit Bus Mode (External Data Bus 16-Bit/
Multiplex Mode)
External Interrupt
Block Diagram of DTP/External Interrupt
External Interrupt Operation
External Interrupt Request Level
Operation Process of DTP/External Interrupt
Overview of DTP/External Interrupt
Register List of DTP/external Interrupt
INDEX
....................630
.........460
.........461
...................460
...........................76
2
....................74
OS)
2
OS) Processing
.....................83
2
OS) Status
........................................79
....................................191
........................164
........................168
.................................166
..........................170
........................168
.................................503
...............................502
.............139
................385
....................................191
.................422
..................................425
.............................427
.............427
........................422
.....................423
677